1. Field of the Invention
The present invention relates to a timing controller, an image display device provided with the timing controller, a reset signal output method used for the timing controller, and the like.
2. Description of the Related Art
Recently, reductions in EMI (Electro Magnetic Interference) and power consumption have been demanded due to increased scale of image display devices and increased speeds in clock and data. For fulfilling such demands, digital interfaces between timing controllers and signal-line driving circuits used in the image display devices are replaced from CMOS (Complementary Metal Oxide Semiconductor) types to differential types such as RSDS (Reduced Swing Differential Signal), mini-LVDS (Low-Voltage Differential Signaling), and the like.
The standards of the RSDS and mini-LVDS are announced from National Semiconductor Corporation and Texas Instruments, respectively. Currently, many designers use those standards for the digital interface between the timing controller and the signal-line driving circuit. “Mini-LVDS Interface Specification (SLDA007A-August 2001—Revised July 2003, TEXAS INSTRUMENTS)” is known as the mini-LVDS standard announced from Texas Instruments (Non-Patent Document 1).
FIG. 9 is a time chart showing a part of the standard disclosed in Non-Patent Document 1, in which the lateral axis is the time and the longitudinal axis is the level of each signal. Each of the signals on the longitudinal axis is clock (LVCLKP), a signal of a video data line (LV0), and a signal of a video data line (LVi) from the top in this order. Explanations will be provided hereinafter by referring to FIG. 9.
In a case where the digital interface between a timing controller and a signal-line driving IC is the mini-LVDS, a reset signal (Reset) for driving the signal line is embedded to video data outputted from the timing controller, and transmitted on the video data line (LV0). In the format of the reset signal embedded to the video data, it becomes “Low” after last data of one line (Last Data Bit), and then becomes “Low” for one clock after “High” period (TRST) that satisfies the specification. This timing is the reference generating position of the reset signal (Reset). From the rise of a next clock of this “Low” to the first data of a next line (First Data Bit) is fetched to the signal-line driving IC (Integrated Circuit).
FIG. 10 is a block diagram showing an image display device of Related Technique 1. FIG. 11 is a block diagram showing a signal-line driving IC of Related Technique 1. Hereinafter, explanations will be provided by referring to FIG. 10 and FIG. 11.
The image display device 50 of this case includes a display panel 51, a timing controller 52, a signal-line driving circuit 53, and a scan-line driving circuit 54. The display panel 51 is a liquid crystal display panel, and the image display device 50 is a liquid crystal display device.
Even though not shown in the drawing, the display panel 51 includes: a plurality of scan lines provided at a prescribed interval in a row direction; a plurality of signal lines provided at a prescribed interval in a column direction; liquid crystal cells which are equivalent capacitive loads provided at intersections between the signal lines and scan lines; a common electrode; TFTs (Thin Film Transistors) which drive the corresponding liquid crystal cells; and a capacitor which stores a data charge for one vertical synchronizing period. The signal-line driving circuit 53 is formed with a plurality of signal-line driving ICs 55. The scan-line driving circuit 54 is formed with a plurality of scan-line driving ICs 56. The signal-line driving IC 55 is compatible with the mini-LVDS interface.
The timing controller 52 includes a reset signal generating section 59 which generates the reset signal RST (Reset) at the timing depicted in Non-Patent Document 1 as well as a video data processing section and a timing generating section, not shown. The video data processing section processes video data Data supplied from outside. The timing generating section generates a data latch pulse signal DLP (Data Latch Pulse) and a clock signal HCK (Horizontal Clock) for the signal-line driving IC 55, generates a start pulse signal VSP (Vertical Start Pulse), a clock signal VCK (Vertical Clock), and an output enable signal VOE (Vertical Output Enable) for the scan-line driving IC 56, and generates a polarity reverse signal POL (Polarity Reverse) for AC (alternating current)-driving the liquid crystal display 51. Hereinafter, the data latch pulse signal DLP, the clock signal HCK, the start pulse signal VSP, the clock signal VCK, the output enable signal VOE, and the polarity reverse signal POL are simply referred to as a signal DLP, a signal HCK, a signal VSP, a signal VCK, a signal VOE, and a signal POL, respectively. Further, the timing controller 52 is connected to one side of the display panel 51 via FPCs (Flexible Printed Circuits) 61, 62, and a TCP (Tape Carrier Package) 63, and connected to another side of the display panel 51 via an FPC 64 and a TPC 65. Four ports A, B, C, and D are provided to the timing controller 52, and the FPCs 61, 62 are connected to the ports A, B, C, and D, respectively. The signal-line driving IC 55 is mounted to the TCP 63, and the scan-line driving IC 56 is mounted to the TCP 65. Each of the above-described signals are transmitted on the ports A, B, C, D, the FPCs 61, 62, and the TCPs 63, 65.
In FIG. 10, there are a plurality of signal-line driving ICs 55, scan-line driving ICs 56, FPCs 61, 62, and TCPs 63, 65, respectively. However, reference numerals are applied to only one each of those. Further, while the video data Data and each of the signals DLP, etc., are illustrated to be supplied directly to the TCP 63 in FIG. 10, those are actually supplied to the TCP 63 via each of the ports A, etc., and the FPCs 61, 62 as in the case of the reset signal RST.
Each signal-line driving IC 55 fetches the video data Data outputted from the timing controller 52 at the timings of the signal DLP, the signal POL, and the signal HCK outputted from the timing controller 52. Subsequently, each-signal line driving IC 55 converts the video data Data to a voltage value by each pixel of one line, and supplies the voltages thereof to corresponding pixel electrodes of one line of the display panel 51 via a drain electrode of the TFT. Note here that the TFTs, the pixel electrodes, and the like are the structural elements of the display panel 51 as described above.
Further, as shown in FIG. 11, the signal-line driving IC 55 includes a shift register section 57 and a signal-line output section 58. The output number of the signal-line driving IC 55 is “720” ch (channels). The shift register section 57 performs sequential shift actions by the reset signal RST, the signal HCK, and the signal RL supplied from the timing controller 52. The reset signal RST is embedded to the video data Data as described above. The signal RL is used for setting the shift register which determines the scanning direction. Signals SP1 and SP2 are internal signals of the signal-line driving IC 55, which are start pulse signals.
A plurality of signal-line driving ICs 55 correspond to each of the ports A-D, and the plurality of signal-line driving ICs 55 individually operate by each of the ports A-D. For example, in a case where there are three or more signal-line driving ICs 55 for a single port, the signal-line driving IC 55 operating first reads a prescribed number of data from the video data Data when there is an input of the reset signal RST, and outputs the signal SP2 to the next signal-line driving IC 55. The next signal-line driving IC 55 receives the signal SP2 as the signal SP1, and starts the same action. When the action of the last signal-line driving IC 55 is completed, each of the signal-line driving ICs 55 simultaneously output the read data to the respective signal line. In FIG. 10 and FIG. 11, the signal-line driving IC 55 shifts the action from the left to the right when the signal RL is “1” (referred to as “left-to-right forward scanning action”), and shifts the action from the right to the left when the signal RL is “0” (referred to as “left-to-right reverse scanning action”).
The scan-line driving IC 56 controls all the scan lines of each of the TFTs by a unit of one line by synchronizing with the signal VCK based on the signal VSP, the signal VOE, and the signal VCK outputted from the timing controller 52. That is, the scan-line driving IC 56 sequentially makes each of the TFTs of one line from the top of FIG. 10 conductive, and applies a gradation voltage to the pixel electrodes supplied from the signal-line driving IC 55 at the time of making the TFTs conductive. Note here that the TFTs, the scan lines, the pixel electrodes, and the like are the structural elements of the display panel 51 as described above.
In FIG. 10, the display resolution of the display panel 51 is WUXGA (Wide Ultra eXtended Graphics Array: 1920×1200), the timing controller 52 is of 10-bit output with four ports, and there are eight signal-line driving ICs 55 each with output number of 720 ch. A case of left-to-right reverse scanning action under that condition will be described. In a case where the number of pixels on one line is “1920 (note that one pixel is formed with three sub-pixels)” and the output number of the signal-line driving IC 55 is 720 ch, there is no residual in the output number of the signal-line driving ICs 55 when eight signal-line driving ICs 55 are used (∵1920=720×8÷3). The timing controller 52 is of four-port outputs, so that two each of the signal-line driving ICs 55 are cascade-connected as shown in FIG. 10. The timing controller 52 generates the reset signal RST by the reset signal generating section 59.
FIG. 12 is a time chart showing a signal waveform at the time of executing the left-to-right reverse scanning according to Related Technique 1, in which the lateral axis is the time and the longitudinal axis is the levels of each signal. Each of the signals on the longitudinal axis from the top to the bottom is a clock signal (HCK), output signals of the ports A-D, and an output signal used for the explanation. Hereinafter, explanations will be provided by referring to FIG. 10—FIG. 12.
Since there is no residual in the output number of the signal-line driving ICs 55, the timing regarding the reset signal RST and the video data Data satisfies the standard of Non-Patent Document 1 even at the time of the left-to-right reverse scanning. That is, regarding the output signals of the ports A-D, the reference positions of the reset signals RST coincide with each other, and the time between the reference positions to the start of reading the video data Data also coincide with each other. This makes it possible for the image display device 50 to perform a proper display without any problems.
Next, techniques disclosed in Patent Documents will be described.
The technique disclosed in Japanese Unexamined Patent Publication Hei 11-311763 (Paragraph 009, etc.: Patent Document 1) invalidates the output of a front terminal of a source driver IC by shifting the timing at which the source driver IC reads the data through changing the timing of a start pulse inputted to the source driver IC for an appropriate number of data. Thereby, the remaining terminals of the source driver IC are distributed to the front and rear.
The technique disclosed in Japanese Unexamined Patent Publication 2002-207452 (Paragraphs 0035, 0036, etc.: Patent Document 2) equalizes the output number of the signal-line driving ICs and the input number of the display panel by turning off a part of the outputs of the signal-line driving ICs. This makes it possible to prevent the shift in the display when the scanning direction of the signal lines is reversed.
However, there is an issue in a case where not the signal-line driving IC with 720 ch but a signal-line driving IC with 414 ch is used in the image display device 50 described in FIG. 10-FIG. 12. Such signal-line driving IC is used in a case where there is only the signal-line driving IC with 414 ch that satisfies a specific electric property, in a case where it is less expensive to use the IC with 414 ch, etc. Detailed explanations will be provided hereinafter.
FIG. 13 is a block diagram showing an image display device of Related Technique 2. FIG. 3 is a block diagram showing a signal-line driving IC of Related Technique 2 (i.e., the signal-line driving IC of Related Technique 2 is in the same structure as that of a signal-line driving IC according to a first exemplary embodiment of the invention). Hereinafter, explanations will be provided by referring to FIG. 13 and FIG. 3. Same reference numerals as those of FIG. 10 and FIG. 11 are applied to the same components in FIG. 13 and FIG. 3.
In an image display device 70, the display resolution of the display panel 51 is WUXGA, the timing controller 52 is of 10-bit output with four ports, and there are fourteen signal-line driving ICs 75 each with output number of 414 ch. That is, a signal-line driving circuit 73 is formed with fourteen signal-line driving ICs 75. As shown in FIG. 3, the signal-line driving IC 75 includes a shift register section 77 and a signal-line output section 78. Other structures are the same as those of Related Technique 1 described above.
In a case where the number of pixels in the WUXGA resolution on one line is “1920” and the output number of the signal-line driving IC 75 is “414” ch, there are residuals of “36” ch in the output number of the signal-line driving ICs 55 when fourteen signal-line driving ICs 75 are used.
The residual outputs of the signal-line driving ICs 75 are not connected to the signal lines of the display panel 51, so that those are normally open-processed and become dummy terminals. Therefore, it is necessary to perform dummy-terminal processing on some of the fourteen signal-line driving ICs 75. FIG. 13 is a case where dummy processing is performed on the fourth and eleventh signal-line driving ICs 75 from the left side of the signal-line driving circuit 73. In that case, the thirty-six residual outputs are the issue in a case of left-to-right reverse scanning even though those are not an issue in a case of left-to-right forward scanning FIG. 14 is a time chart showing a signal waveform at the time of executing the left-to-right reverse scanning according to Related Technique 2, in which the lateral axis is the time and the longitudinal axis is the levels of each signal. Each of the signals on the longitudinal axis is a clock signal (HCK) and output signals of the ports A-D from the top to the bottom. Hereinafter, explanations will be provided by referring to FIG. 13, FIG. 3, and FIG. 14.
At the time of the left-to-right reverse scanning, sequential shift actions are executed from an output terminal s414 of the signal-line driving IC 75 to an output terminal s1. At this time, the eighteen outputs (six pixels) of output terminals s397-s414 of the fourth and eleventh signal-line driving ICs 75 from the left side are the dummy terminals, so that those are not connected to the display panel 51. FIG. 14 shows signal waveforms thereof.
Therefore, the first six pixels of the ports A and C of the timing controller 52 are not connected to the display panel 51, so that there is no display on those pixels. The outputs of the ports B and D are all connected to the display panel 51, so that there is a proper display provided therewith without any problems. Since the first six pixels of the ports A and C of the timing controller 52 cannot provide a display, the image display device 70 comes to provide a fault display that is shifted laterally for six pixels.
As described above, the image display device 70 formed with the timing controller 52 cannot provide a proper display with the left-to-right reverse scanning action, when there are residual outputs of the signal-line driving ICs 75 generated depending on a combination of the display resolution and the output number of the signal-line driving ICs 75. That is, the signal-line driving IC that can be used for the products of the specification where the left-to-right reverse scanning actions are essential is limited to the type with which there is no residual in the number of outputs. Thus, it lacks flexibility in terms of designing, e.g., signal-line driving ICs with still better electric property cannot be used. Further, the signal-line driving components cannot be shared with other products, which hinders a reduction in the costs.
Further, the techniques disclosed in Patent Documents 1 and 2 do not use the mini-LVDS interface standard, so that it is not possible with those to drive signal lines corresponding to that standard.
It is therefore an exemplary object of the present invention to provide a timing controller and the like, which can display an image properly regardless of the scanning direction even when an image display device is formed by using signal-line driving ICs having residual output terminals that are not connected to the signal lines.